Difference between revisions of "Kknee1"
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Revision as of 13:59, 26 April 2010
- garden12 ; emg_2009 ; Enc_2010 ; AKENC ; Kknee1 ; Br46_v1 gps1 ; lifefix ; battery ; loadwasher ; elecdog ; Brushless_control ; ceb_misc_prj ; pf_top_nav ; T
Contents
todo
- order housings for all the connectors, including the 6x1mm
assembly notes
- white LED has black text marking the index pin (die is faintly visible also)
- add note to assembly docs
- QY1 needs to be installed upside down and slightly rotated, as pins 2 and 3 need to be flipped
- add note to assembly docs
errors
- PIC32 FUP, and SWIFI outputs need their serial ports swapped
- PIC32 FUP needs PGC and PGD swapped
dsPIC in system timing (SVN revision 81)
- w/debug code appx 2.52mS
- debug code off : 2.26mS
- motor commands off : appx 2.18mS
PIC32 timing (SVN revision 81)
Using 32 bit code generation and -Os optimization
- 2ws flash 78.64MHz - 500uS - fastest 100% in spec
- 2ws flash, 83MHz - 472uS
- 3ws flash, 83MHz - 500uS
- 2ws flash, 103.2MHz = 382uS
Using 16 bit code generation and -Os optimization
- 2ws flash, 103.2MHz = 422uS
Using 32 bit code generation and NO optimization
- 2ws flash, 103.2MHz = 540uS
Using 16 bit code generation and NO optimization
- 2ws flash, 103.2MHz = 566uS
Using 32 bit code generation and -OS "fastest" optimization
- 2ws flash, 103.2MHz = 388uS
Using 32 bit code generation and -O2 optimization
- 2ws flash, 103.2MHz = 390uS
Using 32 bit code generation and -O1 optimization
- 2ws flash, 103.2MHz = 390uS
flash overclock
DS specs : 0WS for 0-30MHz, 1WS for 30 to 60MHz, and 2WS for 80MHz
- 0WS flash, 41.7MHz - 818uS
- 1ws flash, 83MHz - 440uS
- 2ws flash, 125MHz - 316uS
- 3ws flash, 140MHz - 300uS
PLL configs
CLK = 14.74MHz
- 41Mhz = CLK / 3 * 17 / 2
- 78MHz = CLK / 3 * 16
- 83MHz = CLK / 3 * 17
- 103MHz = CLK / 3 * 21
- 125Mhz = CLK / 2 * 17
- 140MHz = CLK / 2 * 19