BLMD6c
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- AKCPU2z BLMD6c BLFT6c PSER1c Imu_2010 Emg_2009 Ric Upd_pcb
Taken from :http://scripts.mit.edu/~biomechatronics/wiki/index.php?title=BLMD6C
Contents
changes
blmd6c
- On MD board, replace RI2 with 40k, or RI1 with 5k ??? (M2-M10 built this way, may have correct IW1-5, M1)
blft6c
- On FET board, replace RB1 with large resistance to identify board (M2-M10 have 1M, M1, I1-I5 have random values)
- Add 3.0V SOD-123 zener (top) between RT1 and CO1. Zener bar on RT1 side. (M8,M10,I4 corrected)
- FUTURE : Replace ZAP50 with ZAP25.
- User loop code to collect many samples from ADC1 (DMA in scatter gather mode)
- Redo motor temp sensing circuit
ADISR2
- Correct AVCC error on ADISR2 - install jumper
- increase local supply voltage to 5.6V, (put 3.9M across 200k) - or use 187 to 191k
Connectors
encoder / hall
(Has 5V pullups, and 5 to 3.3V level shifters)
PE1
- PB3 - ENC.N
- PB4 - ENC.A
- PB5 - ENC.B
PE2
(Has 5V pullups, otherwise no protection)
- PD5 - HALL1
- PD6 - HALL2
- PD7 - HALL3
analog inputs
- NOTE CH0 is the muxed channel
- AN0 (CH1) - MOT.U
- AN1 (CH2) - V.IBAT
- AN2 (CH3)- MOT.W
- AN9 - HALF.AVCC5
- AN10 - VBUS
- AN12 - M.TEMP
- AN13 - ANA.IN (FET)
blft6c
RB1
- I1 : 1M
- I2 : 665K
- I3 : 330K
- I4 : 200K
- I5 : 100k
- M1 : 2.0M
calc values of r for desired ADC readings. adc = 8:32:1024' r = 1024 * Vcc5 * RB2 ./ (Vcc3.3 * adc)' - RB2 r = 1024 * 5 * 100 ./ (3.3 * adc)' - 100
cables
hall to BLMD6c
- 2 (4-23-08) used on ALHPA3
- 3 untested
- 4 untested
- 5 seems to have intermittent connection
- 6 (4-23-08) used on ALPHA1 for now.
spec
INTERRUPT PRIORITY
- TOP : current control loop
- SS CN interrupt
- ASYNC serial ports
- TIMER3 - used for main loop timing, and disable the current loop controller if there is no SPI activity
SPI slave
init
- setup DMA channel for SPI slave. No interrupt on the DMA
- config SPI to be a slave that uses SS as CS
- config CN11 (SS) to generate interrupt on both edges, make sure this int priority less than the PWM and serial
data
- SS is asserted, causes CN interrupt which loads TX data into DMA controller
- expect that 10uS is required for the loading
- assume F SCLK is 1MHz, 16uS per word - thus the magic word is transfered during this interval
- CN is negated, CN interrupt verifies that SPI DMA completed, and if Magic match - transfers Rx data into local registers, or increments SPI error count
