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| | *{{T_lab_topnav}} | | *{{T_lab_topnav}} |
| | *{{T_lab_pca}} | | *{{T_lab_pca}} |
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| − | Taken from :http://scripts.mit.edu/~biomechatronics/wiki/index.php?title=BLMD6C
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| − |
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| − | =changes=
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| − | ==blmd6c==
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| − | * On MD board, replace RI2 with 40k, or RI1 with 5k ??? (M2-M10 built this way, may have correct IW1-5, M1)
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| − |
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| − | ==blft6c==
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| − | * On FET board, replace RB1 with large resistance to identify board (M2-M10 have 1M, M1, I1-I5 have random values)
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| − | * Add 3.0V SOD-123 zener (top) between RT1 and CO1. Zener bar on RT1 side. (M8,M10,I4 corrected)
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| − | * FUTURE : Replace ZAP50 with ZAP25.
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| − | * User loop code to collect many samples from ADC1 (DMA in scatter gather mode)
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| − | * Redo motor temp sensing circuit
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| − |
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| − | ==ADISR2==
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| − | * Correct AVCC error on ADISR2 - install jumper
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| − | * increase local supply voltage to 5.6V, (put 3.9M across 200k) - or use 187 to 191k
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| − |
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| − | =Connectors=
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| − |
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| − | == encoder / hall ==
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| − | (Has 5V pullups, and 5 to 3.3V level shifters)
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| − | ===PE1===
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| − | * PB3 - ENC.N
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| − | * PB4 - ENC.A
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| − | * PB5 - ENC.B
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| − |
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| − | ===PE2===
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| − | (Has 5V pullups, otherwise no protection)
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| − | * PD5 - HALL1
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| − | * PD6 - HALL2
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| − | * PD7 - HALL3
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| − |
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| − | ==analog inputs==
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| − | * NOTE CH0 is the muxed channel
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| − | * AN0 (CH1) - MOT.U
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| − | * AN1 (CH2) - V.IBAT
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| − | * AN2 (CH3)- MOT.W
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| − | * AN9 - HALF.AVCC5
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| − | * AN10 - VBUS
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| − | * AN12 - M.TEMP
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| − | * AN13 - ANA.IN (FET)
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| − |
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| − | =blft6c=
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| − | ==RB1==
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| − | * I1 : 1M
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| − | * I2 : 665K
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| − | * I3 : 330K
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| − | * I4 : 200K
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| − | * I5 : 100k
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| − | * M1 : 2.0M
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| − |
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| − | calc values of r for desired ADC readings.
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| − | adc = 8:32:1024'
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| − |
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| − | r = 1024 * Vcc5 * RB2 ./ (Vcc3.3 * adc)' - RB2
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| − | r = 1024 * 5 * 100 ./ (3.3 * adc)' - 100
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| − |
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| − | =cables=
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| − |
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| − | ==hall to BLMD6c==
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| − | * 2 (4-23-08) used on ALHPA3
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| − | * 3 untested
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| − | * 4 untested
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| − | * 5 seems to have intermittent connection
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| − | * 6 (4-23-08) used on ALPHA1 for now.
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| − |
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| − |
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| − | =spec=
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| − |
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| − | == INTERRUPT PRIORITY ==
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| − | * TOP : current control loop
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| − | * SS CN interrupt
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| − | * ASYNC serial ports
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| − |
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| − | * TIMER3 - used for main loop timing, and disable the current loop controller if there is no SPI activity
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| − |
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| − | ==SPI slave==
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| − |
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| − | ===init===
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| − | * setup DMA channel for SPI slave. No interrupt on the DMA
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| − | * config SPI to be a slave that uses SS as CS
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| − | * config CN11 (SS) to generate interrupt on both edges, make sure this int priority less than the PWM and serial
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| − |
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| − |
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| − | ===data===
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| − | * SS is asserted, causes CN interrupt which loads TX data into DMA controller
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| − | * expect that 10uS is required for the loading
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| − | * assume F SCLK is 1MHz, 16uS per word - thus the magic word is transfered during this interval
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| − | * CN is negated, CN interrupt verifies that SPI DMA completed, and if Magic match - transfers Rx data into local registers, or increments SPI error count
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