Difference between revisions of "Kknee1"
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*QY1 needs to be installed upside down and slightly rotated, as pins 2 and 3 need to be flipped | *QY1 needs to be installed upside down and slightly rotated, as pins 2 and 3 need to be flipped | ||
**add note to assembly docs | **add note to assembly docs | ||
− | + | =AKENCxx interface= | |
+ | # GND (blk) -> PENC1.7 | ||
+ | # +V (red) -> PENC1.6 | ||
+ | # NC | ||
+ | # NC | ||
+ | # AN0 (blk) -> PENC1.4 | ||
+ | # DIG1 (grn) -> PENC1.5 | ||
=PCBs= | =PCBs= | ||
*http://bmech2.media.mit.edu/pcbs/kknee1/ | *http://bmech2.media.mit.edu/pcbs/kknee1/ |
Revision as of 22:33, 3 July 2010
- BiomechDocs BL Knee PFresearchE
- Biomech Documentation links:
- AKCPU2z BLMD6c BLFT6c PSER1c Imu_2010 Emg_2009 Ric Upd_pcb
- kknee1 knee2 P32_paper_project Pic32
Contents
todo
assembly notes
- white LED has black text marking the index pin (die is faintly visible also)
- add note to assembly docs
- QY1 needs to be installed upside down and slightly rotated, as pins 2 and 3 need to be flipped
- add note to assembly docs
AKENCxx interface
- GND (blk) -> PENC1.7
- +V (red) -> PENC1.6
- NC
- NC
- AN0 (blk) -> PENC1.4
- DIG1 (grn) -> PENC1.5
PCBs
errors
- PIC32 FUP, and SWIFI outputs need their serial ports swapped
- PIC32 FUP needs PGC and PGD swapped
dsPIC in system timing (SVN revision 81)
- w/debug code appx 2.52mS
- debug code off : 2.26mS
- motor commands off : appx 2.18mS
PIC32 timing (SVN revision 81)
Using 32 bit code generation and -Os optimization
- 2ws flash 78.64MHz - 500uS - fastest 100% in spec
- 2ws flash, 83MHz - 472uS
- 3ws flash, 83MHz - 500uS
- 2ws flash, 103.2MHz = 382uS
Using 16 bit code generation and -Os optimization
- 2ws flash, 103.2MHz = 422uS
Using 32 bit code generation and NO optimization
- 2ws flash, 103.2MHz = 540uS
Using 16 bit code generation and NO optimization
- 2ws flash, 103.2MHz = 566uS
Using 32 bit code generation and -OS "fastest" optimization
- 2ws flash, 103.2MHz = 388uS
Using 32 bit code generation and -O2 optimization
- 2ws flash, 103.2MHz = 390uS
Using 32 bit code generation and -O1 optimization
- 2ws flash, 103.2MHz = 390uS
flash overclock
DS specs : 0WS for 0-30MHz, 1WS for 30 to 60MHz, and 2WS for 80MHz
- 0WS flash, 41.7MHz - 818uS
- 1ws flash, 83MHz - 440uS
- 2ws flash, 125MHz - 316uS
- 3ws flash, 140MHz - 300uS
PLL configs
CLK = 14.74MHz
- 41Mhz = CLK / 3 * 17 / 2
- 78MHz = CLK / 3 * 16
- 83MHz = CLK / 3 * 17
- 103MHz = CLK / 3 * 21
- 125Mhz = CLK / 2 * 17
- 140MHz = CLK / 2 * 19
PIC32 DOCS
- PIC32 starter kit
- PIC32 USB starter kit
- file:///C:/Program%20Files%20%28x86%29/Microchip/MPLAB%20C32/doc/README.html
- http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2615&dDocName=en532454&redirects=c32
- http://www.johnloomis.org/microchip/docs/32-bit-Peripheral-Library-Guide.pdf
notes
052710
- MC firmware : on bmech2, ricpf, trunk, MC; used vlist:ak_p32.vlist
status
- SN1 : use for dev;
ECO1
- rotate and reverse QY1
ECO2
- install jumper from C84 to PSW2.1 (brings Vsup to the SWIFI side connectors.)
ECO3
- install 20K between pins 8 and 9 of PKNE1
- install Schottky between CY1.1 (cathode) and QY1.2
- reduce RY1 to ~1k